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tb6504f/fg 2006-3-6 1 toshiba bi ? cmos integrated circuit silicon monolithic tb6504f/fg pwm chopper type bipolar stepping motor driver the tb6504f/fg is pwm chopper type sinusoidal micro step bipolar stepping motor driver. sinusoidal micro step operation is accomplished only a clock signal inputting by means of built ? in hard ware. features z 1 chip bipolar sinusoidal micro step stepping motor driver. z output current up to 150 ma z pwm chopper type. z structured by high voltage bi ? cmos process technology. z forward and reverse rotation are available. z 2, 1 ? 2, w1 ? 2, 2w1 ? 2 phase 1 or 2 clock drives are selectable. z package : ssop24 ? p ? 300 ? 1.00 z input pull ? up resistor equipped with reset and enable terminal : r = 200 k ? (typ.) z output monitor available with mo.i o(mo) = 2 ma max. z reset and enable are avail able with reset and enable. weight : 0.32 g (typ.) TB6504FG: the TB6504FG is a pb-free product. the following conditions apply to solderability: *solderability 1. use of sn-37pb solder bath *solder bath temperature = 230c *dipping time = 5 seconds *number of times = once *use of r-type flux 2. use of sn-3.0ag-0.5cu solder bath *solder bath temperature = 245c *dipping time = 5 seconds *the number of times = once *use of r-type flux www..net
tb6504f/fg 2006-3-6 2 block diagram pull ? up resistance pin (20), (21) : 200 k ? (typ.) pin (6), (18) : non connection www..net
tb6504f/fg 2006-3-6 3 pin function pin no. symbol functional description 1 ck1 clock signal input terminal. truth table a 2 m1 excitation control input. 3 m2 excitation control input. truth table b 4 ref in v nf control input. high level ; v nf = 0.5 v, low level ; v nf = 0.25 v 5 mo monitor output. 6 nc no connection. 7 v cc supply voltage terminal for contol circuit. 8 v mb supply voltage terminal for motor drive. 9 b output b 10 pg ? b power gnd 11 nfb b ? ch current detection terminal. 12 b output b 13 a output a 14 nfa a ? ch current detection terminal. 15 pg ? a power gnd 16 a output a. 17 v ma supply voltage terminal for motor drive. 18 nc no connection. 19 s ? gnd signal gnd. 20 reset reset signal input terminal. 21 enable enable signal input terminal. truth table a 22 osc sawtooth oscilation terminal. 23 cw / ccw forward rotation / re verse rotation input terminal. 24 ck2 clock signal input terminal. truth table a pin connection (top view) note: nc : no connection www..net
tb6504f/fg 2006-3-6 4 truth table a input ck1 ck2 cw / ccw reset enable mode h l h l cw l l h l inhibit (note) h l h l ccw l l h l inhibit (note) h h h l ccw l h h l inhibit (note) h h h l cw l h h l inhibit (note) x x x l l initial x x x x h z truth table b initial mode input m1 m2 mode (excitation) mode i out (a) i out (b) l l 2 phase 2 phase 100% ? 100% h l 1 ? 2 phase 1 ? 2 phase 100% 0% l h w1 ? 2 phase w1 ? 2 phase 100% 0% h h 2w1 ? 2 phase 2w1 ? 2 phase 100% 0% excitation 2 phase excitation (m1 : l, m2 : l, cw mode) 1 ? 2 phase excitation (m1 : h, m2 : l, cw mode) z : high impedance x : don?t care note: please don?t use inhibit mode. www..net
tb6504f/fg 2006-3-6 5 w1 ? 2 phase excitation (m1 : l, m2 : h, cw mode) www..net
tb6504f/fg 2006-3-6 6 2w1 ? 2 phase excitation (m1 : h, m2 : h, cw mode) www..net
tb6504f/fg 2006-3-6 7 output current vector orbit (normalize to 90 for each one step) rotation angle vector length ideal tb6504f/fg ideal tb6504f/fg 0 0 0 100 100.00 D 1 11.25 12.41 100 102.39 D 2 22.5 27.78 100 100.22 D 3 33.75 34.39 100 101.80 D 4 45 45 100 102.53 141.42 5 56.25 55.61 100 101.81 D 6 67.5 65.22 100 100.22 D 7 78.75 77.59 100 102.39 D 8 90 90 100 100.00 D 1 ? 2, w1 ? 2, 2w1 ? 2, phase 2 phase www..net
tb6504f/fg 2006-3-6 8 output circuit input circuit ck1, ck2, cw / ccw, m1, reset , enable : terminal osc : terminal m2, ref in : terminals www..net
tb6504f/fg 2006-3-6 9 osc frequency calculation sawtooth osc circuit consists of q 1 through q 4 and r1 through r4. q 2 is turned ?off? when v osc is less than the voltage of 2.5 v + v be q 2 approximately equal to 2.85 v. v osc is increased by c osc charging through r1. q 3 and q 4 are turned ?on? when v osc becomes 2.85 v (higher level.) lower level of v (22) pin is equal to v be q 2 + v sat q 4 approximately equal to 1.4 v. v osc is calculated by following equation. )] 1 r c t exp( [1 5 osc v osc y y y y y y ? ? = (1) assuming that v osc = 1.4 v (t = t 1 ) and = 2.85 v (t = t 2 ) c osc is external capacitance connected to pin (22) and r1 is on ? chip 10 k ? resistor. therefore, osc frequency is calculated as follows. ) 5 1.4 1 ( n r1 c t osc 1 ? ? = l (2) ) 5 2.85 1 ( n r1 c t osc 2 ? ? = l (3) ) ) 5 2.85 1 ( n r1 ) 5 1.4 1 ( n r1 ( c 1 t t 1 f osc 1 2 osc ? ? ? = ? = l l ) f : (c (khz) c 5.15 1 osc osc = www..net
tb6504f/fg 2006-3-6 10 enable and reset function and mo signal fig.1 1 ? 2 phase drive mode (m1 : h, m2 : l) enable signal disables only output signal. internal logic functions are proceeded by ck signal without regard to enable signal. therefore, output current is initia ted from the proceeded timing poin t of internal logic circuit after release of disable mode. fig.1 shows the enable functions, when the system is selected in 1 ? 2 phase drive mode. as reset is low, the decoder is initialized and mo is low. after reset is high, the motion is resumed fr om next clock as shown in fig.2. fig.2 1 ? 2 phase drive mode (m1 : h, m2 : l) mo (monitor output) signals is used as rotation and initial signal for stable rotation checking. www..net
tb6504f/fg 2006-3-6 11 absolute maximum ratings (ta = 25c) characteristic symbol rating unit v cc 5.5 v m (opr) v cc ? 0.3~10 supply voltage v m (max) 18 v i o (max) 150 output current i o ( ? ) 2 ma input voltage v in ~v cc v 0.59 (note 1) power dissipation p d 0.83 (note 2) w operating temperature t opr ? 10~70 c storage temperature t stg ? 55~150 c feed back voltage v i 1.0 v note 1: no heat sink note 2: with heat sink (50 50 1.6 mm cu 10%) recommended operating conditions (ta = ? 10~70c) characteristic symbol test circuit test condition min typ. max unit supply voltage v cc (opr) D D 4.5 5.0 5.5 v output voltage v m (opr) D D 5.5 D 8.0 v output current i out D D D D 120 ma input voltage v in D D D D v cc v clock frequency f clock D D D D 5 khz osc frequency f osc D D 15 D 80 khz www..net
tb6504f/fg 2006-3-6 12 electrical characteristics (unless otherwise specified, ta = 25c, v cc = 5 v, v m = 8 v) characteristic symbol test circuit test condition min typ. max unit high v in (h) 3.5 D v cc +0.4 input voltage low v in (l) gnd ? 0.4 D 1.5 v input hysteresis voltage v h 1 m1, m2, cw / ccw, ref in enable , ck1, ck2, reset D 600 D mv i in ? 1 (h) m1, m2, ref in, v in = 5.0 v D D 100 na i in ? 1 (l) enable , v in = 0 v, reset internal pull ? up resistor 5 25 50 a input current i in ? 2 (l) 1 source type, v in = 0 v D D 100 na i cc1 output open reset : h enable : l (2, 1 ? 2 phase excitation) D 10 18 i cc2 output open (w1 ? 2, 2w1 ? 2 phase excitation) reset : h enable : l D 10 18 i cc3 reset : l, enable : h D 5 D quiescent current v cc terminal i cc4 2 reset : h, enable : h D 5 D ma high v nf (h) ref in h r nf = 5 ? , c osc = 0.0033 f 0.45 0.5 0.55 comparator reference voltage low v nf (l) 3 ref in l r nf = 2.5 ? , c osc = 0.0033 f 0.22 0.25 0.28 v output differential ? v o D b / a, c osc = 0.0033 f r nf = 2.5 ? , ref in = l ? 10 D 10 % v np (h) ? v nf (l) ? v nf D v nf (l) / v nf (h) c osc = 0.0033 f 43 50 57 % maximum osc frequency f osc (max.) D D 100 D D khz minimum osc frequency f osc (min.) D D D D 10 khz osc frequency f osc D c osc = 0.0033 f 31 44 70 khz v oh (mo) D i oh = ? 40 a 4.5 4.9 v cc output voltage v ol (mo) D i ol = 40 a gnd 0.1 0.5 v www..net
tb6504f/fg 2006-3-6 13 output block characteristic symbol test circuit test condition min typ. max unit upper side v sat u1 D 0.90 1.25 lower side v sat l1 i out = 0.12 a D 0.22 0.37 upper side v sat u2 D 0.83 D output saturation voltage lower side v sat l2 4 i out = 0.06 a D 0.12 D v upper side v f u1 D 1.18 1.8 diode forward voltage lower side v f l1 5 i out = 0.12 a D 0.92 1.6 v i m1 enable : ?h? level reset : ?l? level output open D D 50 a output dark current (a + b channels) i m2 enable : ?l? level reset : ?h? level output open, 2 phase excitation mode D 8 28 nf terminal current i nf 2 enable : ?l? level reset : ?h? level output open 1 2.5 7 ma 2 w 1 ? 2 w 1 ? 2 1 ? 2 = 0 D 100 D 2 w 1 ? 2 D D = 1 / 8 D 100 D 2 w 1 ? 2 w 1 ? 2 D = 2 / 8 86 91 96 2 w 1 ? 2 D D = 3 / 8 79 84 89 2 w 1 ? 2 w 1 ? 2 1 ? 2 = 4 / 8 67.5 72.5 77.5 2 w 1 ? 2 D D = 5 / 8 52.5 57.5 62.5 2 w 1 ? 2 w 1 ? 2 D = 6 / 8 37 42 47 2 w 1 ? 2 D D vector 3 = 7 / 8 ref in : l rnf = 2.5 ? c osc = 0.0033 f l = 10 mh/r = 0.5 ? 17 22 27 a ? b chop ? ping current (note) 2 phase excitation mode vector D D D D 100 D % note: maximum current ( = 0) : 100% 2w1 ? 2 : 2w1, 2 phase excitation mode w1 ? 2 : w1, 2 phase excitation mode 1 ? 2 : 1, 2 phase excitation mode www..net
tb6504f/fg 2006-3-6 14 characteristic symbol test circuit test condition min typ. max unit 2 w 1 ? 2 w 1 ? 2 1 ? 2 = 0 D 100 D 2 w 1 ? 2 D D = 1 / 8 D 100 D 2 w 1 ? 2 w 1 ? 2 D = 2 / 8 D 91.2 D 2 w 1 ? 2 D D = 3 / 8 D 84.2 D 2 w 1 ? 2 w 1 ? 2 1 ? 2 = 4 / 8 D 73.6 D 2 w 1 ? 2 D D = 5 / 8 D 59 D 2 w 1 ? 2 w 1 ? 2 D = 6 / 8 D 44.6 D 2 w 1 ? 2 D D = 7 / 8 ref in : l rnf = 3.3 ? cosc = 0.0033 f l = 20 mh/r = 60 ? D 25.6 D a ? b chop ? ping current (note) 2 phase excitation mode vector vector 3 D D 100 D % ? = 0 / 8 ? 1 / 8 D 0 D ? = 1 / 8 ? 2 / 8 10 22.5 35 ? = 2 / 8 ? 3 / 8 5 17.5 30 ? = 3 / 8 ? 4 / 8 16.25 28.75 41.25 ? = 4 / 8 ? 5 / 8 25 37.5 50 ? = 5 / 8 ? 6 / 8 26.25 38.75 51.25 feed back voltage step ? v nf D ? = 6 / 8 ? 7 / 8 ref in : l rnf = 2.5 ? c osc = 0.0033 f 37.5 50 62.5 mv t r D 0.3 D t f r l = 2 ? , v nf = 0 v, c l = 15 pf D 2.2 D t plh D 1.5 D t phl ck ~ output D 2.7 D t plh D 5.4 D t phl osc ~ output D 6.3 D t plh D 2.0 D t phl reset ~ output D 2.5 D t plh D 5.0 D output tr switching characteristics t phl 7 enable ~ output D 6.0 D s upper side i oh D D 50 output leakage current upper side i ol 6 v m = 18 v D D 50 a note: maximum current ( = 0) : 100% 2w1 ? 2 : 2w1, 2 phase excitation mode w1 ? 2 : w1, 2 phase excitation mode 1 ? 2 : 1, 2 phase excitation mode www..net
tb6504f/fg 2006-3-6 15 test circuit 1. : v in (h), (l) , i in (h), (l) test circuit 2. : i cc , i m , i nf test circuit 3. : v nf (h), (l) tb6504f/fg tb6504f/fg tb6504f/fg www..net
tb6504f/fg 2006-3-6 16 test circuit 4. : v ce (sat) upper, lower note: calibrate output current becomes 0.06 a (or 0.12 a) with this resistor. test circuit 5. : v f ? u , v f ? l test circuit 6. : i oh , i ol note: not to take a gnd with any non ? connecting pins. tb6504f/fg tb6504f/fg tb6504f/fg www..net
tb6504f/fg 2006-3-6 17 ac electrical character istic, test circuit ck (osc) ? out www..net
tb6504f/fg 2006-3-6 18 www..net
tb6504f/fg 2006-3-6 19 application circuit note 1: schottky diode (u1gwj49) to be connected additionally between each output (pin 16 / 13 / 12 / 9) and gnd for preventing punch ? through current. note 2: gnd pattern to be laid out at one point in order to prevent common impedance. note 3: capasitor for noise suppression to be connected between the power supply (v cc , v m ) and gnd to stabilize the operation. note 4: utmost care is necessary in the design of the output, v cc , v m , and gnd lines since the ic may be destroyed by short-circuiting between outputs, air contamination f aults, or faults due to improper grounding, or by short-circuiting between contiguous pins. tb6504f/fg www..net
tb6504f/fg 2006-3-6 20 package dimensions ssop24 ? p ? 300 ? 1.00 unit : mm weight : 0.32 g (typ.) www..net
tb6504f/fg 2006-3-6 21 notes on contents 1. block diagrams some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes. 2. equivalent circuits the equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. 3. timing charts timing charts may be simplified for explanatory purposes. 4. application circuits the application circuits shown in this document are provided for reference purposes only. thorough evaluation is required, especially at the mass production design stage. toshiba does not grant any license to any industrial property rights by providing these examples of application circuits. 5. test circuits components in the test circuits are used only to obtain and confirm the device characteristics. these components and circuits are not guaranteed to prevent malfunction or failure from occurring in the application equipment. ic usage considerations notes on handling of ics [1] the absolute maximum ratings of a semiconductor de vice are a set of ratings that must not be exceeded, even for a moment. do not exceed any of these ratings. exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion. [2] use an appropriate power supply fuse to ensure that a large current does not continuously flow in case of over current and/or ic fa ilure. the ic will fully break down when used under conditions that exceed its absolute maximum ratings, when the wiring is routed improperly or when an abnormal pulse noise occurs from the wiring or load, caus ing a large current to continuously flow and the breakdown can lead smoke or ignition. to minimize the effects of the flow of a large current in case of breakdown, appropriate settings, such as fuse ca pacity, fusing time and in sertion circuit location, are required. [3] if your design includes an inductive load such as a motor coil, incorporate a protection circuit into the design to prevent device malfunction or breakdown caused by the current resulting from the inrush current at power on or the negative current resulting from the back electromotive force at power off. ic breakdown may cause injury, smoke or ignition. use a stable power supply with ics with built-in protection functions. if the power supply is unstable, the protection function may not operate, causing ic breakdown. ic breakdown may cause injury, smoke or ignition. [4] do not insert devices in the wrong orientation or incorrectly. make sure that the positive and negative terminals of power supplies are connected properly. otherwise, the current or power consumption may exceed the absolute maximum rating, and exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion. in addition, do not use any device that is applied the current with inserting in the wrong orientation or incorrectly even just one time. www..net
tb6504f/fg 2006-3-6 22 points to remember on handling of ics (1) heat radiation design in using an ic with large current flow such as power amp, regulator or dr iver, please design the device so that heat is appropriately radiated, not to exceed the specified junction temperature (t j ) at any time and condition. these ics generate heat even during normal use. an inadequate ic heat radiation design can lead to decrease in ic life, de terioration of ic characteristics or ic breakdown. in addition, please design the device taking into considerate the effect of ic heat radiation with peripheral components. (2) back-emf when a motor rotates in the reverse direction, stops or slows down abruptly, a current flow back to the motor?s power supply due to the effect of back-emf. if the curr ent sink capability of the power supply is small, the device?s motor power supply and output pins might be ex posed to conditions beyond maximum ratings. to avoid this problem, take the effect of back-em f into consideration in system design. www..net
tb6504f/fg 2006-3-6 23 www..net

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